Semiconductor-on-insulator (SOI) technology, which represents an advance over traditional bulk semiconductor processes, was first commercialized in the late 1990s. The defining characteristic of SOI technology is that the semiconductor region in which circuitry is formed is isolated from bulk substrate by an electrically insulating layer.
As used herein and in the appended claims, the region in which signal-processing circuitry is formed on an SOI structure is referred to as the active layer of the SOI structure. When reference is made particularly to the layer of active semiconductor material that forms the active devices in an SOI structure the term active device layer is used instead.
The insulating layer of an SOI substrate is typically silicon-dioxide. The reason silicon-dioxide is chosen is that it can be formed on a wafer of silicon by oxidizing the wafer and is therefore amenable to efficient manufacturing. The advantageous aspects of SOI technology stem directly from the ability of the insulator layer to electronically isolate the active layer from bulk substrate. However, as described below the insulator layer that is the source of this advantageous aspect creates significant problems in terms of the thermal performance of SOI technology.
An example prior art SOI structure 100 is shown in FIG. 1. The structure 100 includes a substrate layer 101, an insulator layer 102 and an active layer 103. The substrate layer 101 is typically a semiconductor material such as silicon. The insulator layer 102 is a dielectric which is often silicon-dioxide formed through the oxidation of a portion of the substrate layer 101. The active layer 103 includes a combination of dopants, dielectrics, polysilicon, metal layers, passivation, and other layers that are present after circuitry has been formed therein. This circuitry may include metal wiring 104 (in a metal interconnect layer 105); passive devices such as resistors, capacitors, and inductors; and active devices such as a transistor 106 (in an active device layer 107.
As used herein and in the appended claims, the “top” or “front” of the structure 100 references a top surface 108 while the “bottom” or “back” of the structure 100 references a bottom surface 109. This orientation scheme persists regardless of the relative orientation of the structure 100 to other frames of reference, and the removal of layers from, or the addition of layers to the structure 100. Therefore, the active layer 103 is always “above” the insulator layer 102. In addition, a vector originating in the center of the active layer 103 and extending towards the bottom surface 109 will always point in the direction of the “back side” or “bottom” of the structure 100 regardless of the relative orientation of the structure 100 to other frames of references, and the removal of layers from, or the addition of layers to the structure 100.
SOI devices are imbued with the ability to enhance and preserve the electrical characteristics of their active devices as described above. However, the introduction of the insulator layer (e.g. 102) creates a significant problem in terms of the device's ability to dissipate heat. Due to the increasing miniaturization of the devices in integrated circuits, a greater number of heat generating devices must be pressed into a smaller and smaller area. In modern integrated circuits, the heat generation density of circuitry can be extreme. The introduction of the insulator layer 102 exacerbates this problem because the thermal conductivity of the insulator layer 102 is generally much lower than that of a standard bulk substrate.
As mentioned previously, silicon-dioxide is the ubiquitous insulator layer in modern SOI technology. At a temperature of 300 degrees Kelvin (K), silicon-dioxide has a thermal conductivity of roughly 1.4 Watts per meter per Kelvin (W/m/K). A bulk silicon substrate at the same temperature has a thermal conductivity of roughly 130 W/m/K. The nearly 100-fold reduction in heat dissipation performance exhibited by SOI technology is highly problematic. A high level of heat in an integrated circuit can shift the electrical characteristics of its devices outside an expected range causing critical design failures. Left unchecked, excess heat in a device can lead to permanent and critical failures in the form of warping or melting of materials in the device's circuitry.
Layer transfer devices can incorporate SOI technology. Layer transfer can be described with reference to a layer transfer structure 200 in FIG. 2. In an example layer transfer process for creating the structure 200, a handle wafer 201 is bonded to the top surface of an SOI wafer 202 (e.g. similar to SOI structure 100, FIG. 1). The SOI wafer 202, in this example, has a buried insulator layer 203 and an active layer 204 (with an active device layer 205 and a metal interconnect layer 206). The handle wafer 201 comprises a handle substrate layer 207 and a bonding material layer 208. After bonding, an underlying substrate layer (e.g. similar to 101) is commonly removed, such that the buried insulator layer 203 is exposed and forms a new back side surface 209 of the structure 200. Additional layers can be deposited on the back side surface 209 of the buried insulator layer 203 to form a barrier against contamination from the environment.
The dissipation of heat in layer transferred structures poses a significant problem. Although heat can be directed out of the system from the active layer through the buried insulator layer 203, there is a limit to how many contacts can be made through the buried insulator layer 203. Heat must therefore be conducted laterally through the structure 200 before it can reach a point where it can diffuse rapidly in a vertical direction out of the system. Lateral heat conduction is extremely difficult in SOI and layer transferred devices. The reason for this difficulty is that each layer is extremely thin and therefore has very high thermal resistivity in a lateral direction. A layer having a thickness of tens of micrometers (μm) would probably be sufficient to provide a highly thermally conductive lateral path through the layer capable of keeping peak temperatures in the active layer 204 below the temperature at which degradation mechanisms can become a reliability problem. However, most layers in a layer transfer device are less than 1 μm thick. Producing thicker layers is more costly in terms of the time it takes to deposit, grow or implant the layer. Since the production of semiconductor structures requires the use of extremely expensive capital equipment, procedures that take large amounts of time are prohibitively expensive. Thicker layers also introduce complexity into the process because planarization is more difficult with thicker layers.